edi8l24128c 1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs white electronic designs corp. reserves the right to change products or speci?cations without notice. january 2002 rev. 1 128kx24 asynchronous sram, 5v description the edi8l24128cxxbc is a 5v, three megabit sram constructed with three 128kx8 die mounted on a multi- layer laminate substrate. with 12 to 15ns access times, x24 width and a 5v operating voltage, the edi8l2418c is ideal for creating a single chip memory solution for the motorola dsp5600x or a two chip solution for the analog devices sharc? dsp. the single or dual chip memory solutions offer improved system performance by reducing the length of board traces and the number of board connections compared to using multiple monolithic devices. for example, the capacitance load on the data lines for the bga package is 58% less than a monolithic soj solution. the jedec standard 119 lead bga provides a 44% space savings over using 128kx8, 300mm wide sojs and the bga package has a height of 100mm compared to 148mm for the soj packages. features ? 128kx24 bit cmos static ? random access memory array ? fast access times: 12 and 15ns ? master output enable and write control ? ttl compatible inputs and outputs ? fully static, no clocks ? surface mount package ? 119 lead bga (jedec mo-163), no. 391 ? small footprint, 14mm x 22mm ? multiple ground pins for maximum noise immunity ? single +5v (10%) supply operation ? dsp memory solution ? motorola dsp5600x? ? analog devices sharc? fig. 1 pin configuration pin description 1 2 3 4 5 6 7 a nc a 0 a 1 a 2 a 3 a 4 nc b nc a 5 a 6 e a 7 a 8 nc c dq 12 nc nc nc nc nc dq 0 d dq 13 v cc gnd gnd gnd v cc dq 1 e dq 14 gnd v cc gnd v cc gnd dq 2 f dq 15 v cc gnd gnd gnd v cc dq 3 g dq 16 gnd v cc gnd v cc gnd dq 4 h dq 17 v cc gnd gnd gnd v cc dq 5 i nc gnd v cc gnd v cc gnd nc j dq 18 v cc gnd gnd gnd v cc dq 6 k dq 19 gnd v cc gnd v cc gnd dq 7 l dq 20 v cc gnd gnd gnd v cc dq 8 m dq 21 gnd v cc gnd v cc gnd dq 9 n dq 22 v cc gnd gnd gnd v cc dq 10 o dq 23 nc nc nc nc nc dq 11 p nc a 9 a 10 w a 11 a 12 nc q nc a 13 a 14 g a 15 a 16 nc a0-16 address inputs e# chip enables w# master write enable g3 master output enable dq0-23 common data input/output v cc power (+5v10%) gnd ground nc no connection a 0-a16 g# w# e# dq0-dq7 dq8-dq15 dq16-dq23 128k x 24 memory array
edi8l24128c 2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs white electronic designs corp. reserves the right to change products or speci?cations without notice. january 2002 rev. 1 absolute maximum ratings* recommended operating conditions voltage on any pin relative to v ss -0.5v to 7.0v operating temperature t s (ambient) commercial industrial 0c to + 70c -40c to +85c storage temperature -55c to +125c power dissipation 3 watts output current. 20 ma junction temperature, t j 175c *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this speci?cation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics (vcc = 5v, t a = 25c) capacitance ( f=1.0 mhz , v in =v cc or v ss ) note: for t ehqz , t ghqz and t wlqz , cl = 5pf figure 2 parameter symbol min typ max units supply voltage v cc 4.5 5.0 5.5 v supply voltage v ss 0 0 0 v input high voltage v ih 2.2 v cc +0.3 v input low voltage v il -0.3 +0.8 v ac test conditions input pulse levels v ss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load figure 1 parameter symbol max unit address lines c l 8 pf data lines c d / q 10 pf write & output enable line w#, g# 8 pf chip enable lines e# 8 pf truth table e# w# g# mode output power h x x standby high z i cc 2 , i cc 3 l h h output deselect high z i cc 1 l h l read data out i cc 1 l l x write data in i cc 1 parameter symbol conditions min type max units operating power supply current i cc 1 w# = v il , i i / o = 0ma, min cycle 200 270 ma standby (ttl) power supply current i cc 2 e# ? v ih , v in ? v il or v in ? v ih , f = 0mhz 45 ma full standby power cmos i cc 3 e# ? v cc -0.2v 10 ma supply current v in ? v cc -0.2v or v in ? 0.2v input leakage current i li v in = 0v to v cc 10 a output leakage current i lo v i / o 0v to v cc 10 a output high voltage v oh i oh = -4.0ma 2.4 v output low voltage v ol i ol = 8.0ma 0.4 v fig. 1 fig. 2 d o u t 3 0 p f v l = 1 . 5 v r l = 5 0 ? z 0 = 5 0 ? d o u t 4 8 0 ? 2 5 5 ? 5 p f v c c
edi8l24128c 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs white electronic designs corp. reserves the right to change products or speci?cations without notice. january 2002 rev. 1 ac characteristics read cycle parameter symbol 12ns 15ns units jedec alt. min max min max read cycle time t avav t rc 12 15 ns address access time t avqv t aa 12 15 ns chip enable access time t elqv t acs 12 15 ns chip enable to output in low z 1 t elqx t clz 3 3 ns chip disable to output in high z 1 t ehqz t chz 6 7 ns output hold from address change t avqx t oh 3 3 ns output enable to output valid t glqv t oe 6 7 ns output enable to output in low z 1 t glqx t olz 0 0 ns output disable to output in high z 1 t ghqz t ohz 6 7 ns 1. this parameter is guaranteed by design but not tested. parameter symbol 12ns 15ns units jedec alt. min max min max write cycle time t avav t wc 12 15 ns chip enable to end of write t elwh t eleh t cw t cw 9 9 9 9 ns ns address setup time t avwl t avel t as t as 0 0 0 0 ns ns address valid to end of write t avwh t aveh t aw t aw 9 9 10 10 ns ns write pulse width t wlwh t eleh t wp t wp 10 10 11 11 ns ns write recovery time t whax t ehax t wr t wr 0 0 0 0 ns ns data hold time t whdx t ehdx t dh t dh 0 0 0 0 ns ns write to output in high z 1 t wlqz t whz 0 6 0 7 ns data to write time t dvwh t dveh t dw t dw 6 6 7 7 ns ns output active from end of write 1 t whqx t wlz 3 3 ns ac characteristics write cycle 1. this parameter is guaranteed by design but not tested.
edi8l24128c 4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs white electronic designs corp. reserves the right to change products or speci?cations without notice. january 2002 rev. 1 fig. 3 write cycle w# controlled fig. 4 write cycle e# controlled e# a t avav t el wh t a vwh t wl wh t a vwl t whax w# high z da ta vali d t wlqz t whqx t dvw h t whdx q d a t av el high z t avav t eleh e# t av eh t ehax w# t wleh t ehdx t dveh q da ta v alid d address 1 address 2 t avav d ata 1 d ata 2 t av qv t av qx a q fig. 2 timing waveform read cycle t ghqz t elqv t elqx e# g# q t ehqz a t avav t glqv t glqx t av qv read cycle 2 (w# high) read cycle 1 (w# high; g, e low)
edi8l24128c 5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs white electronic designs corp. reserves the right to change products or speci?cations without notice. january 2002 rev. 1 0.866 bsc pin 1 index 0.551 bsc 0.1 10 max. 0.028 max. r.060 max. (4x) 0.050 typ 0.800 bsc 0.300 bsc package 391: 119 lead bga jedec mo-163 ordering information part number speed (ns) package no. edi8l24128c12bi 12 391 edi8l24128c15bi 15 391 industrial (-40 c to +85c) all dimensions are in inches part number speed (ns) package no. edi8l24128c12bc 12 391 EDI8L24128C15BC 15 391 commercial (0 c to +70c)
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